Flat no-leads packaging solutions, such as Quad-Flat No-Leads (QFN) packages offer several benefits. For example, QFN packages can provide reduced lead inductances, a small, nearly chip scale footprint, a thin profile, and low weight. QFN packages also offer perimeter or edge input/output (I/O) pads, thereby facilitating printed circuit board (PCB) trace routing. Moreover, QFN packages may include an exposed conductive die paddle enabling good thermal and electrical performance.
As semiconductor technologies become more complex, the number of required I/O terminals on semiconductor packages continues to increase. Conventional QFN packaging solutions have included single-row or multi-row QFN packages. Such conventional QFN packages are typically limited to less than 100 leads in single row perimeter designs, and less than 165 leads for dual row designs. As designs move to the current minimum terminal pitch of approximately 0.4 mm, a conventional approach to accommodating the increased number of I/O terminals is to move to a QFN package having a larger body size. However, moving to a larger QFN body size undesirably results in a costlier, thicker, and heavier semiconductor package.